In recent years, electronic components with higher functionality have been demanded in response to size reduction and improved functionality of electronic equipment such as mobile phones and digital cameras. Particularly, as lamination techniques for semiconductor chips have been improved, stacked semiconductor modules in which a plurality of semiconductor chips are stacked and integrated have been developed with higher functionality.
For example, Japanese Patent Laid-Open No. 2004-363126 discloses the configuration of a stacked semiconductor module. In this configuration, a first semiconductor package in which a first semiconductor chip is mounted and a second semiconductor package in which a second semiconductor chip is mounted are stacked.
In the manufacturing of such a stacked semiconductor module, a test is conducted after the semiconductor packages are stacked. When the semiconductor module is judged to be defective in this test, the whole stacked semiconductor module has to be discarded as a reject or it is necessary to temporarily separate the mounting portions of the first and second semiconductor packages, package the semiconductor packages again, and then conduct a test again, resulting in a low yield in the manufacturing process.
Thus it is necessary to conduct a test for guaranteeing the reliability of semiconductor devices before stacking the semiconductor devices. For this reason, semiconductor devices which can be tested thus have been demanded.
For example, Japanese Patent Laid-Open No. 2004-281633 discloses the configuration of a stacked semiconductor module in which a plurality of chips are stacked and mounted. Each of the chips has mounting terminals and test terminals for quality inspection on the first major surface, mounting pads to be connected, on the second major surface, to the mounting terminals of another chip, and test pads electrically connected to the test terminals on the first major surface.
With this configuration, it is possible to conduct a test in a state in which the test pads of a first chip mounted on a substrate and the test terminals of a second chip mounted on the first chip are joined to each other. In other words, the test can be conducted by inputting a test signal to the test terminals of the first chip from the substrate and then inputting the test signal to the test terminals of the second chip through the test pads of the first chip.
When the semiconductor module is found to be non-defective in the test, the tested second chip is moved on the first chip and the mounting terminals of the second chip are connected to the mounting pads of the first chip to mount the second chip.
In this stacked semiconductor module, the chips are mounted directly on the substrate but packages having chips mounted therein are not stacked on top of each other.
Japanese Patent Laid-Open No. 2002-83897 discloses a configuration which can easily test electrical characteristics. In this configuration, a wiring pattern is formed on a substrate having a larger outside shape than a semiconductor chip, the semiconductor chip is mounted on the substrate, and the semiconductor chip and the first and second terminals of the substrate are electrically connected to each other.
The first terminals are disposed outside a region where the semiconductor chip is mounted, and are exposed on one side of the substrate. The second terminals are disposed in the region where the semiconductor chip is mounted, and are exposed, on the other side of the substrate, in through holes formed on the substrate.
In this semiconductor device, the first terminals can be used for electrical connection to other members, and the second terminals can be used for testing electrical characteristics. However, a test covering the first terminals cannot be conducted.
Japanese Patent Laid-Open No. 9-223725 discloses a grid array semiconductor package. In this semiconductor package, a semiconductor device has signal pins arranged in a grid array on the underside of the body, and is surface mounted by joining the signal pins and the circuit pattern of a circuit board. The semiconductor device includes contact pads electrically connected to the signal pins and disposed on the front side of the body.
This configuration facilitates a continuity test for checking the connection of the signal pins and the circuit pattern of the circuit board during surface mounting, and facilitates an electrical test conducted on the semiconductor package after the semiconductor package is fabricated.
However, when such a configuration is used for a stacked semiconductor module, the contact pads used as connecting terminals for stacking may be scratched by probes coming into contact with the contact pads, so that a faulty connection may occur. Further, since each semiconductor device has to be tested, the cost of testing equipment increases.
Japanese Patent Laid-Open No. 2003-124274 discloses a configuration for testing a semiconductor wafer. In this configuration, an electrode pad for a connecting terminal is provided in each chip region on the semiconductor wafer and a test pad is provided outside the chip region.
Thus it is possible to reduce the area of the test pad on the semiconductor chip, thereby reducing the size of the semiconductor chip and the size of a semiconductor device using the semiconductor chip.
However, in a stacked semiconductor device, a three-dimensional wiring configuration on a substrate for wiring is important in quality, which has not been particularly disclosed.
The present invention has been devised to solve the foregoing problems. An object of the present invention is to provide a substrate for wiring, a semiconductor device for stacking using the same, and a stacked semiconductor module which can facilitate a test on the connecting terminals of the semiconductor device for stacking used for the stacked semiconductor module, improve the reliability of the stacked semiconductor module, and achieve an inexpensive manufacturing process.